OR Gate: What is it? (Working Principle & Circuit Diagram)

What is an OR Gate?

An OR gate implements the inclusive logical OR operation. Its output is high when at least one input is high. The output is low only when every input is low. Like an AND gate, an OR gate can have two or more inputs and has one output.

For inputs restricted to numeric values 0 and 1, OR gives the same result as taking the maximum input value. This is a useful comparison, but the gate implements a Boolean function rather than a general maximum calculation.

The standard symbol for a two-input OR gate is shown above.

OR Gate Truth Table

2 Input OR Gate

Truth tables list a circuit’s output for every possible input combination. The two-input table has four rows. Only A = 0 and B = 0 produces output 0.

3 Input OR Gate

A three-input OR gate has eight possible input combinations. Its output is 1 for every row except 000.

The symbol above adds a third input to the same OR-gate shape.

The three-input truth table is shown above. It implements Y = A + B + C.

Related topics in digital electronics include NOT gates, NAND gates, NOR gates, XOR gates and XNOR gates.

OR Gate Circuit Diagram

Like an AND gate, an OR function can be demonstrated with a diode-resistor network or a transistor circuit. These examples are simplified positive-logic implementations.

OR Gate Diode Circuit Diagram

The diagram uses two diode inputs and a pull-down resistor.

If A and B are both 0 V, the resistor holds output X near 0 V. If either input is +5 V, its diode becomes forward biased and raises the output voltage. A conducting diode is not an ideal short circuit, so X remains below the active input voltage.

Using the simplified constant-drop model for a silicon diode, a forward drop of about 0.6 to 0.7 V leaves approximately 4.4 to 4.3 V at X from a 5 V input. The actual voltage depends on diode current, temperature, the resistor and the load. It is a valid logic high only if it meets the receiving circuit’s specified input threshold.

When both inputs are +5 V, both diodes can conduct and X remains approximately one forward drop below the inputs in this simplified model.

When A and B are both at 0 V, the diodes do not raise X and the pull-down resistor holds the output at logic low.

OR Gate Transistor Circuit Diagram

The diagram also shows an OR function made with a transistor network. It uses input transistors followed by an inverting output stage.

When A and B are both 0 V, T₁ and T₂ are off. Resistor R raises the base drive for T₃, turning it on. Current then flows through resistor R′ and T₃, pulling output X low.

When T₃ is driven into saturation, T₃ pulls X near ground but not exactly to 0 V. The relevant voltage drop is the transistor’s collector-emitter saturation voltage, not its base-emitter forward voltage. Whether that low voltage is valid depends on the receiving logic family’s input-low limit. The circuit also needs correctly chosen base and collector resistors.

If A, B or both inputs are high, the corresponding T₁ or T₂ transistor turns on. This pulls the shared control node toward ground and removes base drive from the output transistor.

With the control node low, T₃ turns off. T₃ therefore stops pulling X toward ground, and resistor R′ pulls X toward +5 V. This produces the high output required when one or more inputs are high. The available output voltage and current still depend on the load and component values.

OR Gate Integrated Circuits

OR gates are available in TTL and CMOS logic families. TTL means transistor-transistor logic. CMOS means complementary metal-oxide-semiconductor and uses complementary MOSFET devices. Supply limits and input thresholds depend on the exact part number and family.

The CD4000 CMOS family includes several OR-gate configurations used in digital electronic circuits. CD4071B contains four two-input gates, CD4075B contains three three-input gates and CD4072B contains two four-input gates. Check the manufacturer’s data sheet for package and electrical details.

OR Gate IC 4071

CD4071B is a 14-pin IC containing four independent two-input OR gates. For the standard pinout, pin 14 is VDD and pin 7 is VSS. Texas Instruments specifies a recommended 3 V to 18 V supply range for its CD4071B; 5 V is one supported operating point, not the maximum.

Gate 1 uses inputs 1 and 2 with output 3. Gate 2 uses inputs 5 and 6 with output 4. Gate 3 uses inputs 8 and 9 with output 10. Gate 4 uses inputs 12 and 13 with output 11. Confirm this top-view pinout against the data sheet before wiring the package.

OR Gate IC 7432

The 74LS32 belongs to the low-power Schottky TTL family and contains four two-input positive-OR gates. Its internal transistor technology differs from CMOS. The broader 7432 family name covers several logic-family variants, so use the data sheet for the exact OR gate part fitted.

The 74HC32 is a high-speed CMOS quad OR gate, while the 74LVC32A is a lower-voltage CMOS variant. Their supply ranges, logic thresholds and output current ratings differ from 74LS32. For the standard 14-pin 74LS32 pinout, pin 1 and 2 feed output 3; pin 4 and 5 feed output 6; pin 9 and 10 feed output 8; and pin 12 and 13 feed output 11.

Pin 7 is ground and pin 14 is VCC. Use the exact manufacturer and suffix when selecting limits because similarly named families are not electrically interchangeable.

Texas Instruments specifies 4.75 V to 5.25 V as the recommended VCC range for the commercial SN74LS32. Its data sheet separately lists absolute maximum ratings, which are not normal operating targets. Keep every input within the limits for the exact powered device and never assume that one family’s supply range applies to another.