A Comprehensive Guide to Digital Logic Gates

A digital logic gate maps one or more binary input states to an output state according to a Boolean function. Gates form combinational circuits and, with feedback or storage elements, sequential circuits. This article covers common gate functions, truth tables, transistor logic families and practical loading limits.

What is a Digital Logic Gate?

A digital logic gate treats each valid input as LOW or HIGH and produces an output defined by its function. Logic 0 and logic 1 are abstract states represented by specified voltage ranges. The limits depend on the logic family, supply and loading; LOW is not always exactly 0 V and HIGH is not always +5 V.

A gate may have one or more inputs and one or more outputs, though the common gates below have one output. A truth table lists the output for every valid input combination. One input gives two rows, while two inputs give four.

Seven common functions are NOT, AND, OR, NAND, NOR, XOR and XNOR. Buffers, tri-state outputs and more complex standard-logic functions also exist. Boolean algebra describes the logical behaviour independently of the electrical technology used to build it.

Basic Logic Gates

NOT, AND and OR form a functionally complete set: together they can express any Boolean function. The term basic refers to that algebraic role, not to the internal complexity of a physical integrated circuit.

NOT Gate

A NOT gate, or inverter, has one input and one output. It produces the complement of its input: 0 becomes 1 and 1 becomes 0. The and truth table link gives more detail on this form of representation.

Input	Output
0	1
1	0

AND Gate

An AND gate can have two or more inputs but only one output. It performs the logical conjunction operation on its inputs. This means that it outputs “1” only if all its inputs are “1”. Otherwise, it outputs “0”. The symbol and truth table for a two-input AND gate is shown below.

Input A	Input B	Output
0	0	0
0	1	0
1	0	0
1	1	1

OR Gate

An OR gate can have two or more inputs but only one output. It performs the logical disjunction operation on its inputs. This means that it outputs “1” if at least one of its inputs is “1”. Otherwise, it outputs “0”. The symbol and truth table for a two-input OR gate is shown below.

Input A	Input B	Output
0	0	0
0	1	1
1	0	1
1	1	1

Universal Logic Gates

NAND and NOR are universal, or functionally complete, because repeated gates of either one type can implement any Boolean function. This does not make every NAND-only or NOR-only circuit smaller, faster or lower-power than another implementation.

NAND Gate

A NAND gate combines an AND gate followed by a NOT gate. It performs the logical negation of the AND operation. It outputs “0” only if all its inputs are “1”; otherwise, it outputs “1”. The symbol and truth table for a two-input NAND gate are shown below.

Input A	Input B	Output
0	0	1
0	1	1
1	0	1
1	1	0

NOR Gate

A NOR gate is a combination of an OR gate followed by a NOT gate. It performs the logical negation of the disjunction operation on its inputs. This means that it outputs “1” only if all its inputs are “0”. Otherwise, it outputs “0”. The symbol and truth table for a two-input NOR gate is shown below.

Input A	Input B	Output
0	0	1
0	1	0
1	0	0
1	1	0

Exclusive Logic Gates

XOR and XNOR are parity functions. They can generate or compare parity bits for error detection, but a parity gate alone does not locate or correct an error.

XOR Gate

An XOR gate outputs 1 when an odd number of inputs are 1. For two inputs, this means the inputs differ. The table below lists all four two-input combinations.

Input A	Input B	Output
0	0	0
0	1	1
1	0	1
1	1	0

XNOR Gate

XNOR outputs 1 when an even number of inputs are 1. With two inputs, equal values 00 and 11 produce 1, while unequal values 01 and 10 produce 0. Its result is the complement of XOR. The compact table groups equal and different input pairs.

Input pair AB	Output	Condition
00 or 11	1	Inputs equal
01 or 10	0	Inputs differ

Implementation of Digital Logic Gates

Logic functions can be implemented with transistors, diodes, relays or other switching technologies. Integrated digital logic now relies mainly on transistor circuits. Bipolar junction transistors (BJTs) underpin TTL families, while complementary metal-oxide-semiconductor circuits use paired MOSFETs.

Transistor-Transistor Logic (TTL)

TTL uses BJTs and resistors to implement logic functions. A BJT has base, collector and emitter terminals. Base drive controls collector current, but a real TTL gate uses multi-transistor input and output stages rather than one ideal switch.

TTL logic devices specify input thresholds VIL and VIH and guaranteed output levels VOL and VOH at stated currents. Cascading is valid only when output guarantees meet the next input’s thresholds and the total input current stays within the output drive rating.

Classic 5 V TTL commonly guarantees an input as LOW at or below 0.8 V and HIGH at or above 2.0 V. The band between those limits is not a guaranteed logic input. Output voltages use separate limits and depend on source or sink current, so 2 V to 5 V is not an output guarantee.

Compared at their rated conditions, classic TTL offers these practical characteristics:

• Mature standard parts have specified propagation delay and established interface rules.
• Fan-out can be calculated from guaranteed output currents and TTL input currents.
• Common 5 V functions remain available for legacy equipment and education.

Design constraints include:

• Bipolar TTL normally draws more static supply current than an equivalent CMOS gate.
• Its static dissipation adds heat even when inputs are not switching.
• Many classic TTL parts use a narrow 5 V supply range; the exact limits come from the part data sheet.

Complementary Metal-Oxide-Semiconductor (CMOS)

CMOS gates use complementary n-channel and p-channel MOSFET networks. Gate-to-source voltage creates an electric field that controls a conductive channel. Whether a device is on depends on transistor type and threshold relative to its source, not simply on the presence or absence of any gate voltage.

Complementary pull-up and pull-down networks connect the output towards the positive rail or ground for each input state. Logic-family compatibility still requires guaranteed input and output levels. DC input current is small, but input capacitance and switching current limit edge rate, delay and practical fan-out.

CMOS input thresholds and valid supply range are family-specific. Some legacy families tolerate supplies up to 18 V, while modern low-voltage families operate near 1 V. A HIGH input need only exceed VIH; it need not equal the supply rail.

CMOS characteristics include:

• Static current can be very low when inputs are at valid rail levels and leakage is controlled.
• Dynamic power rises with supply voltage, switching frequency and load capacitance.
• Input thresholds can provide useful noise margin, but the margin depends on the family and supply.
• Manufacturers offer many families for different supply, speed, drive and translation needs.

Design constraints include:

• Propagation delay is family-specific; modern CMOS can be faster than classic TTL.
• Inputs require ESD-safe handling and must not exceed their absolute maximum voltage.
• Capacitive loading, simultaneous switching, power integrity and unused-input bias need control. CMOS is not inherently less dense than TTL.

Applications of Digital Logic Gates

Logic gates implement combinational decisions and form the hardware used in sequential systems. Examples include:

• Digital circuits: gates implement adders, subtractors, multiplexers, demultiplexers, encoders and decoders. Gates also form parts of latches, flip-flops, counters, registers and processors.
• Computer architecture: gate networks implement datapaths, control logic, memory interfaces and input/output circuits. An instruction set is an architectural specification realised by that hardware.
• Programming languages: Boolean operators describe logical operations in software. Physical gates execute compiled instructions, but a language definition is not itself a gate circuit.
• Cryptography: hardware accelerators combine XOR, substitution, arithmetic, registers and control logic to execute encryption or hashing algorithms.
• Error detection and correction: XOR networks generate parity and CRC terms. Complete Hamming or Reed-Solomon systems also need storage, finite-field logic and decoding control.
• Artificial intelligence: processors and accelerators use digital arithmetic, memory and control circuits built from gates. Gates do not by themselves define a neural network or learning algorithm.

Conclusion

A logic gate implements a Boolean relation between valid input and output states. NOT, AND and OR form one complete set; NAND alone or NOR alone can also express any Boolean function. XOR detects odd parity, while two-input XNOR detects equality. Truth tables must include every input combination. Physical behaviour depends on the chosen family: supply limits, input thresholds, output drive, propagation delay, loading, power and ESD ratings come from the data sheet. TTL remains useful in legacy 5 V systems, while CMOS families cover modern low-power and high-density logic. Reliable designs check electrical compatibility as carefully as the Boolean function.