Basic Digital Counter

A counter is a sequential circuit that advances through a defined state sequence in response to clock events. In digital electronics, counters use flip-flops plus the logic needed to generate each next state. Common implementations use D, T or JK flip-flops.

One flip-flop stores one bit and has two states, 0 and 1. When configured to toggle on every active clock edge, it forms a modulo-2 counter and divides the clock frequency by two.

Two flip-flops can represent a two-bit binary count from 0 to 3, giving four states and a mod-4 sequence. In general, a full n-bit binary counter has 2ⁿ states from 0 to 2ⁿ-1, so its modulus is 2ⁿ rather than n. The required flip-flop inputs depend on type: a JK stage toggles with J = K = 1, while a D stage toggles only when D is driven by the complement of Q. The truth tables in Table I show these different input actions.

On the active clock edge, a D flip-flop copies D to Q. Holding D high sets Q high; it does not keep toggling. To make a D stage toggle, connect D to the complement of Q. A JK flip-flop holds for J = K = 0, resets for J = 0 and K = 1, sets for J = 1 and K = 0, and toggles for J = K = 1. Figure 2 should therefore be read as a toggle concept: the JK connection can use fixed-high J and K inputs, but a D connection needs feedback from the complemented output.

A counter is classified by its clocking, direction, edge sensitivity, modulus and state sequence. Common distinctions include:

1. Asynchronous ripple clocking or synchronous common-clock operation
2. Up, down or selectable up/down counting
3. Positive-edge or negative-edge triggering, as specified by the flip-flop. Timing diagrams, state tables and state diagrams describe the resulting behaviour.

Figure 3 is intended to show a three-bit asynchronous up-counter using positive-edge-triggered stages. It labels D₀, D₁ and D₂ as high, but a real D flip-flop would then set Q high instead of toggling. Each D input must be connected to its own complemented Q output, or the circuit must use toggle-configured T or JK stages. FF1 receives the external clock; FF2 and FF3 receive the complemented output transitions shown by . The first stage follows the external clock while the later stages respond to from the preceding stage. This stage-to-stage clocking makes these flip-flops asynchronous.

Assume the initial state is Q₂Q₁Q₀ = 111. On the first active clock edge, Q₀ toggles from 1 to 0. Its complemented output changes from 0 to 1 and clocks FF2, so Q₁ changes from 1 to 0. The resulting FF2 complement transition clocks FF3, so Q₂ changes from 1 to 0 when changes from 0 to 1. The count therefore rolls over from 111 to 000 after the ripple settles.

On the second active edge, Q₀ toggles from 0 to 1 and its complement changes from 1 to 0. That transition does not clock the positive-edge FF2, so Q₁ stays 0. FF3 also stays unchanged, giving Q₁ = Q₂ = 0 and a count of 001. On the third edge, Q₀ becomes 0 and rises. FF2 then toggles, making Q₁ = 1 while its complement falls. FF3 does not see a positive edge, so the correct third count is 010. The fourth count is 011. On the fifth edge, Q₀ = 0 and rises; Q₁ = 0 and rises. That edge toggles FF3 from 0 to 1, producing 100. Later clocks give 101, 110 and 111, then the eight-state sequence repeats as shown by the state diagram and truth table.


In an n-bit binary ripple counter, the least significant bit with weight 2^o toggles on every clock, and each higher stage divides the preceding stage frequency by two. For example, Q₂ changes when Q₁ produces the active transition represented by . The transition propagates through the flip-flops rather than reaching every stage together, which gives the ripple counter its asynchronous name and cumulative delay.

In an asynchronous counter, clock-to-output delay accumulates as the transition ripples through the stages. A synchronous counter sends the same clock edge to every flip-flop and uses combinational next-state logic, so it avoids cumulative ripple delay. It still has flip-flop and logic propagation delay.

Figure 6 attempts a three-bit synchronous counter. For a D-flip-flop implementation, D₀, D₁ and D₂ must each receive the complete next-state function derived from the desired sequence. The counter can use the same eight states as the asynchronous example, so its state diagram and state table are unchanged even though its circuit is different.
Bit Q₀ toggles on every active clock edge, so D₀ must equal the complement of the present least significant bit, not a permanent high. Bit Q₁ toggles when Q₀ is high, which gives a D next-state function equivalent to Q₀ XOR the present middle bit. Bit Q₂ toggles only when Q₁ and Q₀ are both high. A two-input AND gate can generate that toggle-enable term from Q₀ and Q₁, but a D input must then XOR the term with the stage’s present Q. With the full next-state logic, Figure 6 counts upward from 0 to 7.
In an n-bit synchronous binary up-counter, bit 0 toggles every clock. Each higher bit toggles when every less-significant bit is high. T flip-flops can use those AND terms directly as toggle inputs, and JK flip-flops can use them on both J and K. D flip-flops need the present-state XOR toggle-enable form. All stages sample their inputs on the same clock edge.
A down-counter follows the reverse state sequence and subtracts one per clock. A three-bit down-counter runs from 111 to 000 before wrapping. Its toggle conditions use the required low states of less-significant bits; the complemented outputs shown by can supply those conditions instead of Q. The exact active edge and interstage connection still depend on the flip-flop type.
Other counter sequences include the Ring Counter, Johnson Counter, decade counter and mod-N counter. Control and feedback logic can also provide these variations:

1. An up/down control selects incrementing or decrementing next-state logic
2. Clear, reset, load or preset inputs establish a known initial state as specified by the device
3. Decode and feedback logic can restart the sequence before all 2ⁿ states occur. For example, a three-bit mod-6 counter uses six states, 000 through 101, then returns to 000. The reset or load timing must be designed to avoid unwanted transient states.