JK Flip Flop: What is it? (Truth Table & Timing Diagram)

What is a JK Flip Flop?

A JK flip-flop is defined as a sequential bi-stable single-bit memory device named after its inventor, Jack Kilby. It has one clock input pin (CLK), two data input pins (J and K), and two output pins (Q and Q̅). It can be triggered on the leading edge (positive) or trailing edge (negative) of the clock signal.

JK Flip Flop Circuit

To understand how a JK flip flop works, we need to look at its basic gates. A positive-edge triggered JK flip flop uses AND gates and NOR gates as shown in Figure 2.

In the circuit, the output Q is combined with input K and the clock pulse using AND gate 1 (A₁). Similarly, output Q̅ is combined with input J and the clock pulse using AND gate 2 (A₂).

The output of A₁ goes to one input (X₁) of NOR gate 1 (N₁), and the other input (Y₁) is connected to Q̅. NOR gate 2 (N2) receives its inputs (X2 and Y2) from A₂ and Q, respectively.

Initially let J = K = 0, Q = 0 and Q̅ = 1. Now consider the appearance of positive-edge of the first clock pulse at the CLK pin of the flip-flop. This results in X₁ = 0 and X₂ = 0. Then the output of N₁ will become 0 as X₁ = 0 and Q̅ = 1; while the output of N₂ will become 1 as X₂ = 0 and Q = 0. Thus one gets Q = 0 and Q̅ = 1.

However if one considers the initial states to be J = K = 0, Q = 1 and Q̅ = 0, then X₁ = X₂ = 0 which results in Q = 1 and Q̅ = 0. This indicates that the state of flip-flop outputs Q and Q̅ remains unchanged for the case of J = K = 0.

Now assume that J = 0, K = 1, Q = 0 and Q̅ = 1. Analyzing on the same grounds, one gets X₁ = X₂ = 0 which further results in Q = 0 (and hence Q̅ = 1). For the same case if Q and Q̅ were 1 and 0, respectively, then X₁ = 1 and X₂ = 0 which would result in Q = 0 (and hence Q̅ = 1).

This implies that if J = 0 and K = 1, then the flip-flop resets (Q = 0 and Q̅ = 1).
Next if J = 1, K = 0, Q = 1 and Q̅ = 0, then X₁ = X₂ = 0 which results in Q = 1 (and thus Q̅ = 0). For the same case if Q = 0 and Q̅ = 1, then X₁ = 0, X₂ = 1 which leads to Q̅ = 0 and hence Q is forced to value 1. This means that for the case of J = 1 and K = 0, flip-flop output will always be set i.e. Q = 1 and Q̅ = 0.

Similarly for J = 1, K = 1, Q = 1 and Q̅ = 0 one gets X₁ = 1, X₂ = 0 and Q = 0 (and hence Q̅ = 1); and if Q changes to 0 and Q̅ to 1, then X₁ = 0, X₂ = 1 which forces Q̅ to 0 and hence Q to 1. This indicates that for J = K = 1, flip-flop outputs toggle meaning which Q changes from 0 to 1 or from 1 to 0, and these changes are reflected at the output pin Q̅ accordingly.

However it is to be noted that the state of the flip-flops remains unaltered if there is no rising-edge of the clock at its input.

JK Flip Flop Truth Table

The truth table for a JK Flip Flop has been summarised in Table I below. The waveforms pertaining to the same are presented in Figure 3. Moreover it is to be noted that the working of the negative edge-triggered flip-flop is similar to that of positive-edge triggered one except that the changes occur at the trailing edge of the clock pulse instead of its leading edge.

JK Flip Flop Timing Diagram

From the truth table above one can arrive at the equation for the output of the J K flip-flop as (Table II). This is known as a timing diagram for a JK flip flop.

In addition to the basic input-output pins shown in Figure 1, J K flip-flops can also have special inputs like clear (CLR) and preset (PR) (Figure 4). These can be used to bring the flip-flop to a definite state from its current state.

For example, the output can be made equal to 0 using CLR pin while it can set to 1 using PR pin. However these pins can be either active high (Figure 4a) or active low (Figure 4b) operated.

Figure 5 shows the waveforms for a positive-edge triggered JK flip flop with active high preset and clear pins.

Moreover it is to be noted that these pins can be either synchronous or asynchronous in nature meaning which the clear and set operations occur either depending on the clock (shown by green lines) or no (shown by red lines), respectively.

Further if the preset and clear pins are active low, then the changes observed in the diagram occur at the instant when clear and preset go low instead of high.

There are also D Flip Flops, SR Flip Flops, Active Low SR Flip Flops, and Gated SR Flip Flops.

You can learn more about JK flip flops and other logic gates by checking out our full list of logic gates questions.