- D Flip Flop Definition: A D Flip Flop (also known as a D Latch) is defined as a memory cell that stores the value on the data line, labeled D.
- Active High and Low SR Flip Flops: These flip-flops change state based on complementary inputs, avoiding invalid output conditions.
- Gated D Latch: This type of latch includes an enable (EN) input, allowing the output to follow the input D only when EN is high.
- D Latch Truth Table: The truth table for a D latch shows that when EN is high, the output follows the input D; otherwise, the output remains unchanged.
- Transparent Behavior: When the enable (EN) input is high, the D latch is transparent, meaning the output directly follows the D input.
What is a D Flip Flop (D Latch)?
A D Flip Flop (also known as a D Latch, data, or delay flip-flop) is defined as a type of flip flop that tracks the input and makes transitions that match the input D. The D stands for ‘data’; this flip-flop stores the value on the data line and acts as a basic memory cell.
In an active high SR Flip Flop, when both S (Set) and R (Reset) are 0, the output doesn’t change. When both S and R are 1, the output is unpredictable. In an active low SR Flip Flop, the output remains unchanged when S and R are both 1, and it is unpredictable when S and R are both 0.
So if both inputs of the flip-flop are the same there will either be a No Change or Invalid output condition. If we avoid these conditions of inputs, there will be either SET or RESET conditions.
Many applications only need the SET and RESET conditions of the latch. In these cases, we can use inputs (S and R) that are always the opposite of each other.
This design uses a single input (S) to the latch, with the R input created by inverting S. This single input is called the data input, labeled as D.
This is why this type of single input Flip flop is known as a D-Flip Flop or D Latch. The basic logical representation (i.e. circuit diagram) of a D-flip flop is shown below.
A D latch can be gated. These types of D latches are known as gated D latches.
Gated D Latch
Many applications don’t need separate S and R inputs. Using a D flip-flop, we can avoid the conditions where S = R = 0 and S = R = 1. In a D flip-flop, if D = 1, then S = 1 and R = 0, setting the latch. If D = 0, then S = 0 and R = 1, resetting the latch. This is known as a Gated D Latch.
We can make this latch as gated latch and then it is called gated D-latch. Like gated SR latch gated D flip-flops also have ENABLE input. The difference from the gated S-R latch is that it has only two inputs D and ENABLE. The above said set and reset conditions of the latch is only seen in the latch when the ENABLE or EN input is high.
That means when D = 1 and EN = 1 the gated latch D flip-flop is ENABLE and SET when D = 0 and EN = 1 the latch is ENABLE and RESET but when EN = 0 the latch is DISABLE no question of SET REST. That means at EN = 0, any change in input D does not affect the output (No Change Condition).
Again SET means output Q = 1 and RESET means Q = 0 so Q = D or output follows input when EN is High and this is the reason for which it is that a LOW D input makes Q Low, i.e. resets the flip-flop and a High D input makes Q High, i.e. sets the flip-flop.
In other words, we can say that the output Q follows the D input when EN is High. So, this latch is said to be transparent.
D Flip Flop Truth Table
The logic diagram, the logic symbol, and the truth table of a gated D-latch are shown in the figures below.
There are also JK Flip Flops, SR Flip Flops, and a Clocked SR Latch.
You can learn more about D flip flops and other logic gates by checking out our full list of logic gates questions.
