- D Flip Flop Definition: A D Flip Flop (also known as a D Latch) is defined as a memory cell that stores the value on the data line, labeled D.
- Active High and Low SR Flip Flops: These flip-flops change state based on complementary inputs, avoiding invalid output conditions.
- Gated D Latch: This type of latch includes an enable (EN) input, allowing the output to follow the input D only when EN is high.
- D Latch Truth Table: The truth table for a D latch shows that when EN is high, the output follows the input D; otherwise, the output remains unchanged.
- Transparent Behavior: When the enable (EN) input is high, the D latch is transparent, meaning the output directly follows the D input.
What is a D Latch or D Flip-Flop?
A D latch and a D flip-flop are related one-bit storage elements with different timing. A D latch is level-sensitive and follows its data input while enable is active. A D flip flop is edge-triggered and samples its data input on a specified clock edge. In both names, D means data or delay.
In an active-HIGH SR Flip Flop, S = R = 0 holds the stored state and S = R = 1 is forbidden. In an active low SR Flip Flop, S = R = 1 holds the state and S = R = 0 is forbidden. The forbidden combination asserts set and reset together and can produce an uncertain recovery state.
These matching-input combinations correspond to the Hold and Forbidden cases. Normal set and reset operation asserts only one control at a time.
A D storage element derives complementary set and reset controls from one data input. This arrangement prevents both controls from being asserted together during normal enabled operation.
For an active-HIGH gated S-R core, one path receives D and the other receives inverted D. The external signal is the data input, labelled D.
The diagram below shows the basic logic used to derive complementary inputs from D. Extra gating determines whether the complete circuit operates as a transparent D latch or as part of an edge-triggered D flip-flop.
A D latch includes an enable or latch-enable control. These circuits are known as gated D latches.
Gated D Latch
A gated D latch connects D and its complement to an S-R storage core through enable-controlled gates. When enabled, D = 1 selects the set path and D = 0 selects the reset path. Because D and inverted D cannot have the same valid logic level, the arrangement removes the S-R forbidden combination from normal operation. This is a Gated D Latch.
Like a gated SR latch, an active-HIGH D latch has an ENABLE input. Its external control inputs are D and ENABLE rather than separate S, R and ENABLE signals. Set or reset action reaches the storage core only while ENABLE is HIGH.
When EN = 1, D = 1 makes Q HIGH and D = 0 makes Q LOW. When EN = 0, the input gates are disabled and Q retains the value present when the latch closed. Changes at D during this hold interval do not change Q.
SET means Q = 1 and RESET means Q = 0. While EN is HIGH, Q follows D after the device’s propagation delay. A LOW D therefore drives Q LOW, and a HIGH D drives Q HIGH.
This input-to-output response while EN is HIGH is called transparency. When EN changes LOW, D must satisfy the device’s setup and hold times so the latch stores a defined value. An edge-triggered D flip-flop instead transfers D to Q only on its active clock edge.
D Latch and D Flip-Flop Truth Tables
The logic diagram, symbol and truth table below describe an active-HIGH gated D latch. EN = 1 makes Q follow D, and EN = 0 retains the previous Q. For an edge-triggered D flip-flop, the corresponding table uses the active clock edge instead of an enable level.
Related storage circuits include JK Flip Flops, SR Flip Flops and a Clocked SR Latch.
Use the logic gates questions to practise latch, flip-flop and timing concepts.
