Johnson Counter: A Digital Sequential Logic Circuit

A Johnson counter feeds a shift register’s last-stage inverted output back to the first stage. Other names include twisted ring counter and switch-tail counter. An n-stage design has an intended cycle of 2n states, making it useful for timing sequences and simple decoding rather than ordinary binary-number display.

What is a Johnson Counter?

A Johnson counter is a shift register in which the complement of the final stage is connected to the serial input of the first stage. On each active clock edge, every stored bit shifts by one position and the inverted final bit enters the register.

D flip-flops implement this next-state relation directly. JK flip-flops can also be used when their input logic makes each stage copy the required previous-stage value. All stages normally share the same clock.

A conventional ring counter recirculates the last stage without inversion and has n one-hot states when correctly initialised. A Johnson counter recirculates the inverted value, causing a run of ones to fill the register and then a run of zeros to empty it.

An n-stage Johnson counter visits 2n states in its intended cycle. The full register still has 2^n possible bit patterns, so the other 2^n – 2n patterns are unused and can form illegal cycles. Reset or correction logic is needed when reliable recovery from an unknown state matters.

Preset and clear pins, when present on the chosen flip-flops, establish a known state. The stage outputs are labelled Q1 through Qn, and the feedback signal is the complement of Qn. Commercial Johnson-counter ICs can add master reset, clock inhibit, decoded outputs and circuitry that returns illegal codes to the valid sequence.

How Does a Johnson Counter Work?

Consider the displayed 3-stage counter, starting from 000 and shifting the inverted Q3 value into Q1. The protected table lists the six-state sequence produced by successive active clock edges.

Clock Pulse	Q1	Q2	Q3
0	0	0	0
1	1	0	0
2	1	1	0
3	1	1	1
4	0	1	1
5	0	0	1
6	0	0	0

Starting at 000, ones enter for three clocks until the register reaches 111. Zeros then enter for three clocks until 000 returns. Only one stage changes at each step, including the transition from 001 back to 000, and the complete period is six clock cycles.

Every raw stage output in this 3-stage example repeats once per six input clocks.

Q1, Q2 and Q3 therefore each have frequency fclock/6 and a 50% duty cycle in the ideal sequence. They are not successive f/2, f/4 and f/8 binary-divider outputs.

With the shift convention shown, Q1 changes first, Q2 follows one clock later and Q3 follows Q2 one clock later. One clock equals one-sixth of the output period, or 60 degrees. A lead or lag statement must name the reference waveform and active clock edge.

What are the Advantages and Disadvantages of a Johnson Counter?

A Johnson counter trades binary state efficiency for a regular sequence that can be decoded with little logic:

• Advantages:
  • An n-stage Johnson counter provides 2n valid timing states, compared with n valid one-hot states in an n-stage ring counter.
  • A deliberate clear to all zeros starts the valid sequence and begins filling the register with ones. An arbitrary power-up pattern can still enter an illegal cycle, so the design cannot rely on generic self-starting.
  • Adjacent valid states differ by one bit, giving a Hamming distance of one. This reduces simultaneous internal transitions, but separate logic is still needed to detect or correct illegal states.
  • Adjacent true and complemented stage signals can decode 2n non-overlapping timing slots with simple gates. Raw outputs or decoded cycles can also provide frequency division.
• Disadvantages:
  • The register state does not represent an ordinary binary count, so conversion logic is required when a binary numeric output is needed.
  • A bare counter uses only 2n of its 2^n possible states. Reset or anti-lock logic may be needed to escape unused-state cycles.
  • It uses n flip-flops for 2n timing states. Clock frequency, propagation delay, output loading and decoder hazards must still meet the device data sheet.

What are some Applications of a Johnson Counter?

Johnson counters support timing and sequence functions in digital electronics, including:

• Synchronous decade counter or divider circuit: A five-stage Johnson counter has ten valid states. A device such as the CD4017 adds a decoder so one of ten outputs is high during each clock slot, along with reset, inhibit and carry functions.
• Finite-state machine: The 2n-state cycle can act as a timing-state register for a fixed sequence. Combinational logic decodes required actions, while reset and illegal-state recovery establish deterministic startup.
• Three-phase square wave generator: The raw outputs of a 3-stage counter are 60 degrees apart over the six-clock period. Combining suitable decoded states can form three 120-degree waveforms; the counter outputs alone do not provide that phase set.
• Frequency divider: Each raw stage output in an n-stage ideal cycle repeats at fclock/(2n). Decoded outputs, reset feedback and carry signals can implement other divide-by-N sequences within the device timing limits.

Conclusion

A Johnson counter is an inverted-feedback shift register with 2n valid states for n stages. In the 3-stage example, all raw outputs run at one-sixth of the clock frequency and are separated by one clock, while simple decoding can produce six timing slots. Reset or correction logic matters because unused states can form separate cycles. These properties make Johnson counters useful in decade counters, sequencers and divide-by-N circuits when their non-binary state code suits the design.