- SR Flip Flop Definition: An SR Flip Flop, also known as an SR Latch, is a basic type of flip flop with two inputs (S and R) and two outputs (Q and \overline{Q}).
- Active High SR Latch: Using NOR gates, the latch is active high, meaning it is set when S = 1.
- Active Low SR Latch: Using NAND gates, the latch is active low, meaning it is set when S = 0.
- SET and RESET Conditions: The latch is set (Q = 1) when S = 1 and R = 0, and reset (Q = 0) when S = 0 and R = 1.
- Truth Table: The truth table of the SR Flip Flop shows the different states based on the inputs S and R.
What is an SR Flip Flop?
An SR Flip Flop, more precisely called an SR Latch in the unclocked form shown here, is a one-bit storage circuit. The terms are often used loosely, but a latch responds to input levels while an edge-triggered flip flop changes state only at a clock edge. The latch has set input S, reset input R and complementary outputs Q and 
. Two cross-coupled NAND gates form an active-low version; two cross-coupled NOR gates form the active-high version explained below.
For the NOR latch, S = 1 sets Q to 1 and R = 1 resets Q to 0. With S = R = 0, feedback holds the previous state. A NAND latch normally labels the controls as active-low inputs because driving the relevant input to 0 performs set or reset.
The figures show the cross-coupled gates and the signal labels used in this explanation.
For the NOR circuit, S = 1 and R = 0 sets Q to 1.
- A NOR gate outputs 0 whenever at least one of its inputs is 1.
- With S = 1, gate G2 therefore drives to 0, regardless of the previous value fed back from Q.
- Gate G1 then receives R = 0 and = 0, so its output is
= 1. - The stable outputs Q = 1 and = 0 define the SET state.
For the NOR circuit, S = 0 and R = 1 resets Q to 0.
- A high input on either input of a NOR gate forces that gate’s output low.
- With R = 1, gate G1 drives Q to 0 regardless of the previous value.
- G2 now receives S = 0 and feedback Q = 0, so becomes 1. The stable outputs Q = 0 and = 1 define the RESET state.
When S = 0 and R = 0, the NOR latch holds its previous value.
- First assume the stored value is Q = 1.
- G2 receives S = 0 and Q = 1, so its output is
= 0. - G1 receives R = 0 and = 0, so Q remains
= 1. - Now assume the stored value is Q = 0.
- G2 receives S = 0 and Q = 0, so becomes = 1.
- G1 receives R = 0 and = 1, so Q remains
= 0. - Both valid states therefore persist when S = R = 0. Feedback gives the flip flop or latch its one-bit memory.
When S = 1 and R = 1, the NOR latch enters its forbidden input condition.
- The result does not depend on whether Q was previously 0 or 1.
- S = 1 forces G2 output to
or 0 for the illustrated feedback state. - With R = 1 and feedback = 0, G1 output Q is
or 0. - While S and R both remain 1, Q = 0 and = = 0. The outputs are no longer complements.
- Thus Q and are both 0. If S and R return to 0 together, the cross-coupled path that first changes determines the result; until then, the remaining high input keeps its NOR output at or 0. Small gate-delay differences can make the circuit settle to either valid state or briefly become metastable, so the input combination must be avoided.
The forbidden condition is therefore deterministic while S = R = 1, because both outputs are 0. The uncertainty occurs when both active inputs are released at nearly the same time. This active-high behaviour applies to the NOR SR latch.
The Active Low SR Latch uses the opposite input polarity. Related one-bit storage circuits include D Flip Flops, JK Flip Flops, SR Flip Flops and Clocked SR Flip Flops. Check whether each circuit is level-sensitive or edge-triggered rather than relying on its informal name.
SR Flip Flop Truth Table
The truth table below summarises the active-high NOR SR latch. The 00 input holds the previous state, 10 sets Q, 01 resets Q and 11 is forbidden.
Use the state table when answering logic gates questions, and always note whether the problem uses active-high NOR inputs or active-low NAND inputs.
