- Gated SR Latch Definition: A gated SR latch is defined as a latch that only changes its output state when an enabling signal is present with the required inputs.
- Synchronous Operation: The gated SR latch works synchronously, responding to inputs only when there is a clock pulse.
- Enable Signal: This latch is active when the ENABLE signal is HIGH and inactive when it is LOW, controlling when the latch can change state.
- Level Triggered: Gated SR latches are level-triggered, meaning they respond to inputs only when the clock pulse is high.
- Truth Table Explanation: The truth table for a gated SR latch shows how different input and ENABLE signal combinations affect the output states.
What is a Gated SR Latch?
A gated SR latch adds an enable input to a basic S-R latch. The enable input controls when S and R can change the stored state. The term synchronous SR latch is sometimes used when enable comes from a system clock. The circuit itself remains level-sensitive: it responds throughout the active enable level instead of sampling only at a clock edge.
For the active-HIGH circuit shown here, ENABLE = 0 blocks S and R and Q retains its previous value. ENABLE = 1 passes the input conditions to the latch. S = 1 and R = 0 sets Q, S = 0 and R = 1 resets Q, and S = R = 0 holds the current state. S = R = 1 is forbidden because set and reset are asserted together.
ENABLE can be a general control signal or a clock-derived level. While it is HIGH, a change at S or R can propagate to Q after the gates’ propagation delay. This continuous response during the active level distinguishes the latch from an edge-triggered flip flop. The logical circuit of a gated SR latch or clocked SR flip-flop is shown below.
Gated SR Latch Truth Table
The truth table below combines enable control with the S-R latch states. When ENABLE is LOW, S and R are don’t-care inputs and Q holds. When ENABLE is HIGH, the S-R combinations select hold, set, reset or the forbidden state.
Related storage circuits include D Latches, JK Flip Flops and Active Low SR Flip Flops. Review Gated SR Flip Flops alongside the logic gates questions to practise the enable and S-R input combinations.
