- Gated SR Latch Definition: A gated SR latch is defined as a latch that only changes its output state when an enabling signal is present with the required inputs.
- Synchronous Operation: The gated SR latch works synchronously, responding to inputs only when there is a clock pulse.
- Enable Signal: This latch is active when the ENABLE signal is HIGH and inactive when it is LOW, controlling when the latch can change state.
- Level Triggered: Gated SR latches are level-triggered, meaning they respond to inputs only when the clock pulse is high.
- Truth Table Explanation: The truth table for a gated SR latch shows how different input and ENABLE signal combinations affect the output states.
What is a Gated SR Latch?
A gated SR latch (or clocked SR Latch) can only change its output state when there is an enabling signal along with required inputs. For this reason it is also known as a synchronous SR latch. Conversely, latches that can change its state instantaneously on the application of its required inputs conditions are known as asynchronous latches.
This means the inputs affect the latch only when it is enabled; otherwise, the output state remains unchanged even if the inputs are applied. In other words, the latch is active when the ENABLE signal is HIGH and inactive when it is LOW. This ENABLE signal is applied as clock pulses.
Therefore, a gated SR latch is also called a clocked SR flip-flop or synchronous SR latch. Because it responds to inputs only when the clock pulse is high, it is also known as a level-triggered flip flop. The logical circuit of a gated SR latch or clocked SR flip-flop is shown below.
Gated SR Latch Truth Table
The truth table for a gated SR latch or gated SR flip-flop is shown below.
There are also D Latches, JK Flip Flops, Active Low SR Flip Flops, and Gated SR Flip Flops. You can learn more about clocked SR flip flops and other logic gates by checking out our full list of logic gates questions.
