- Active Low SR Latch Definition: An active low SR latch is a digital storage device that changes its output state based on low (0) input signals.
- SET Condition: The latch sets, or Q becomes 1, when S is 0 and R is 1, demonstrating how input affects output.
- RESET Condition: It resets, meaning Q becomes 0, when R is 0 and S is 1, further showing input-output dynamics.
- Truth Table Clarification: The truth table for the active low sr latch clearly lists all possible input combinations and their effects on the outputs.
- Unpredictable State Warning: It’s crucial to avoid the condition where both S and R are 0 as it leads to unpredictable outputs, highlighting the need for careful input planning.
What is an Active Low SR Latch?
An active-low SR latch is an asynchronous, level-sensitive latch. The circuit responds to input levels without waiting for a clock edge. Two cross-coupled NAND gates form the circuit shown below. Its S and R inputs are active when LOW, so they are often written with bars above the letters or bubbles at the input terminals.
With S = 0 and R = 1, the latch enters the SET state and Q becomes 1.
- A NAND gate produces 1 when either input is 0.
- S = 0 therefore forces the output of G1, Q, to 1 regardless of the feedback input
. - Q feeds G2. With Q = 1 and R = 1, both inputs of G2 are 1, so its output is
or 0. - The SET state has Q = 1 and = 0.
With S = 1 and R = 0, the latch enters the RESET state and Q becomes 0.
- A LOW input at either NAND-gate input forces that gate’s output HIGH.
- R = 0 therefore forces the output of G2, , to 1 regardless of Q.
- The HIGH feedback and S = 1 make both G1 inputs HIGH, so Q becomes 0. The RESET state has Q = 0 and = 1.
With S = 1 and R = 1, neither active-low input is asserted. Feedback then holds the previous state.
- First consider a previously SET latch, where Q = 1.
- R = 1 and Q = 1 make both G2 inputs HIGH. Its output remains or 0.
- S = 1 and the LOW feedback make G1’s output Q remain
or 1. - Now consider a previously RESET latch, where Q = 0.
- R = 1 and Q = 0 make G2’s output remain or 1.
- S = 1 and the HIGH feedback make G1’s output Q remain or 0.
- In both cases, S = 1 and R = 1 retain the stored state.
S = 0 and R = 0 is the forbidden input combination for this active-low NAND latch.
- Apply LOW to both S and R.
- R = 0 forces G2’s output to
or 1, regardless of Q. - S = 0 also forces G1’s output Q HIGH, even though the feedback is 1. Q is therefore
or 1. - Q and are both or 1, so they are no longer complements. The output stays HIGH while R remains LOW.
- When both inputs return HIGH together, propagation-delay differences determine which gate responds first. The feedback input and the output state represented by do not define a guaranteed final state.
While S and R are both 0, Q and its complementary output are both 1. If both inputs are released at nearly the same time, the latch may settle to either valid state and can briefly become metastable. Circuit designers avoid this input combination.
Active Low SR Latch Truth Table
The truth table below summarises the active-low SR latch. LOW-HIGH sets Q. HIGH-LOW resets Q. HIGH-HIGH holds the previous value. LOW-LOW is forbidden.
Related storage circuits include D Latches, JK Flip Flops and Gated SR Latches. The logic gates questions provide further practice with digital-logic concepts.
