Op-Amp Integrator: A Circuit that Performs Mathematical Integration

What is an Op-Amp Integrator?

An op-amp integrator is an inverting operational amplifier (op-amp) circuit whose feedback element is a capacitor. Within the circuit’s linear range, its output voltage equals a scaled, inverted time integral of the input voltage. A constant positive input therefore produces a negative-going output ramp. The scale factor is set by the input resistance and feedback capacitance.

Integrators appear in analog computers, active filters, control loops, dual-slope analog-to-digital converters (ADCs) and waveform generators. A balanced square wave produces a triangular output. A sine wave produces a cosine-shaped output with a 90-degree phase relationship, subject to the circuit’s sign convention and operating limits.

How Does an Op-Amp Integrator Work?

The basic circuit uses an inverting amplifier connection. The input resistor is Rin, and the feedback element is a capacitor C rather than a resistor. Its reactance magnitude is inversely proportional to frequency:

Here, f is frequency in hertz and C is the capacitor’s capacitance in farads. The complex impedance is 1/(j2πfC); the displayed Xc is its magnitude.

The schematic below shows the ideal ground-referenced circuit:

Vin drives the inverting input through Rin. The non-inverting input is connected to ground, so negative feedback holds the inverting node near ground while the op-amp remains linear. This node is called a virtual ground because no direct ground connection exists there. The output Vout drives feedback capacitor C. In a single-supply design, both inputs and the output are instead referenced to a suitable mid-supply voltage.

Apply Kirchhoff’s current law at the inverting node. For an ideal op-amp, no current enters the input pin. The current Vin/Rin must therefore flow through C:

Rearranging the current equation gives the output ramp rate:

The derivative is dVout/dt, not dVin/dt. A larger input voltage produces a steeper ramp, while a larger Rin or C produces a shallower ramp. Integrating from the starting time gives:

V0 is the capacitor’s initial output voltage at t = 0. This initial condition shifts the whole output waveform but does not change the ramp slope.

A reset switch across C can discharge the capacitor and establish V0 before an integration interval. A servo or reference source can set another initial value. An offset-trim potentiometer may cancel a measured DC error, but placing a potentiometer in series with C does not independently set the capacitor’s initial voltage.

What are some Characteristics and Limitations of an Op-Amp Integrator?

The equations above assume infinite open-loop gain and bandwidth, zero input current, zero offset and unlimited output swing. A real circuit integrates only over a finite frequency, amplitude and time range. Its main error sources are:

• Op-amp characteristics: Finite open-loop gain and gain-bandwidth product limit accuracy and phase response. Input offset voltage, noise, input impedance, output-current capability, slew rate and output swing also limit the result. The selected device must operate from the chosen supply and keep its inputs inside their common-mode range.
• Capacitor leakage: Leakage resistance provides an unwanted DC path. Capacitance tolerance, temperature coefficient, dielectric absorption and voltage coefficient can also change the scale factor or retain charge from an earlier signal.
• Input bias current: Bias current and input offset current flow through the input and feedback paths. With no DC feedback resistor, even a small error current continuously charges C and causes an output voltage drop or rise until saturation. A resistance at the non-inverting input can balance source resistance where the op-amp data sheet recommends it.
• Frequency response: The capacitor is approximately an open circuit at DC and its reactance falls as frequency rises. For the ideal circuit, the signal-gain magnitude is 1/(2πfRinC). It rises without limit toward DC in the mathematical model, so any DC input or offset eventually drives a real output to a supply rail.

The ideal magnitude falls by 20 dB per decade, equal to 6 dB per octave, as frequency rises. Its phase is 90 degrees relative to an inverting resistive gain once the polarity convention is included. Real op-amp phase lag, finite loop gain and slew rate add error near the upper operating limit.

The falling magnitude resembles a one-pole low-pass response, but an ideal integrator has no bounded DC passband. At low frequency, offset and DC input create a long ramp that reaches a rail. A practical circuit adds a controlled DC feedback path or uses a surrounding servo loop, and it includes a reset method when the initial condition matters.

How to Improve an Op-Amp Integrator?

The usual practical integrator places a feedback resistor Rf in parallel with C. Rf gives the circuit finite DC gain, limits drift and lets capacitor charge leak away. The circuit acts as an inverting amplifier at low frequency and approaches an integrator above its corner frequency.

Its closed-loop signal gain is:

Zf is the parallel impedance of Rf and Xc, while || denotes a parallel combination. In complex form, Zf = Rf/(1 + j2πfRfC).

At DC, gain is -Rf/Rin. At the corner frequency, its magnitude is Rf/(√2 Rin), not Rf/(2 Rin). Above the corner, capacitor impedance dominates and gain approaches -1/(j2πfRinC). The magnitude then falls toward 20 dB per decade until finite op-amp loop gain, phase shift or slew rate makes the integration error unacceptable.

The corner occurs where the magnitudes of Rf and Xc are equal:

Set fc below the lowest signal frequency that must be integrated. Operating at least one decade above fc gives a close magnitude approximation, but phase and amplitude error still need calculation against the application limit. Rf must also be low enough to prevent output saturation from the worst-case DC input, offset and bias current.

• Adding a resistor in series with the capacitor: A series feedback resistor Rs changes the transfer function to -(Rs + 1/sC)/Rin. It does not create a DC reset path. Instead, it sets a finite high-frequency gain of -Rs/Rin, which can limit high-frequency closed-loop attenuation and noise gain. The shown circuit is:

Its closed-loop gain is:

Here, Zf is the series impedance Rs + 1/(j2πfC). The capacitor term dominates when |Xc| is much larger than Rs, and the circuit then approximates the ideal integrator.

At DC, the capacitor is open and the mathematical gain is unbounded, so a real output saturates. When |Xc| = Rs, the gain magnitude is √2 Rs/Rin. At high frequency, gain approaches Rs/Rin rather than continuing to fall. This network therefore integrates below its transition frequency, subject to low-frequency saturation. It does not have zero DC gain or a separate pole where gain becomes unity.

The displayed ideal-gain equation applies where C is the only feedback impedance or where its impedance dominates another series element. It predicts a 20 dB-per-decade fall. It does not by itself set the usable range. Rin, C, feedback resistors, op-amp loop gain, slew rate, noise and required accuracy set that range together.

How to Design an Op-Amp Integrator?

Start with the input waveform, required output ramp, integration interval, supply rails and error limit. Then choose Rin, C, the DC feedback path and an op-amp whose data-sheet limits cover the full operating range. Check these factors:

• Integration time constant: RC sets the ramp scale, dVout/dt = -Vin/(RC). For a constant input applied for Δt, calculate ΔVout = -VinΔt/(RC). Choose RC from the required output change, not from a rule that it must always exceed the input period. For a practical integrator, also place fc = 1/(2πRfC) below the integration band.
• Output voltage range: Add the worst-case ramp change to the initial or reference voltage. The result must stay inside the op-amp’s linear output range for the actual load and supply. Check input common-mode range, output current and slew rate. Supply voltage divided by RC is not an output-range formula.
• Op-amp characteristics: Use the data sheet, not device age, to select the amplifier. Check total supply range, unity-gain stability, gain-bandwidth product, open-loop gain, slew rate, input offset and drift, bias current, noise, input common-mode range, output swing and load drive. Include capacitor leakage, dielectric absorption and tolerance in the error budget.

What are some Examples of Op-Amp Integrators?

The examples below use a Texas Instruments TLV9002 and assume a ground-referenced dual supply of ±2.5 V, which is 5 V total. The device is rated for 1.8 V to 5.5 V total supply; ±5 V would be 10 V total and is outside its rating. A 5 V single supply can instead use a buffered mid-supply reference. Each example needs a reset or DC feedback path and must keep its output within the data-sheet swing limit.

Example 1: R = 10 kΩ, C = 0.1 μF

RC = 1 ms, so a constant +0.2 V input produces dVout/dt = -200 V/s. For a 200 Hz square wave, each half-cycle lasts 2.5 ms and changes the output by 0.5 V. The resulting triangular waveform is about 0.5 V peak-to-peak when centred correctly. The ideal gain magnitude is unity at 1/(2πRC) = 159 Hz. Choose Rf from the required low-frequency corner, then check output headroom, 1 MHz gain-bandwidth product and 2 V/μs typical slew rate against the TLV9002 data sheet.

Example 2: R = 100 kΩ, C = 0.01 μF

RC is again 1 ms, so the same +0.2 V input and 2.5 ms interval produce the same 0.5 V change in the ideal transfer equation. The source sees ten times more resistance than in Example 1, while the capacitor is one-tenth as large. Bias-current error through Rin, resistor noise, input capacitance and leakage relative to 0.01 μF can therefore differ even though the signal scale factor is the same.

Example 3: R = 1 kΩ, C = 1 μF

RC remains 1 ms, so the ideal ramp scale is unchanged. A +0.2 V input draws 0.2 mA through Rin and still produces a 0.5 V output change over 2.5 ms. The low resistance loads the source more heavily, and a 1 μF capacitor may have more leakage or dielectric absorption than a smaller precision capacitor. Do not apply the previously stated ±50 V input: it exceeds the TLV9002 supply and input ratings and would force 50 mA through 1 kΩ.

Conclusion

An op-amp integrator converts input voltage into an inverted output ramp with scale factor 1/(RC). The ideal circuit uses Rin and a feedback capacitor. Practical designs add a DC feedback or reset path so offset and bias current do not leave the output at a rail. Integrators support waveform generation, analog computation, control loops, filters and integrating ADCs.

Choose components from the required input, output change, time interval and frequency band. Then verify:

• Integration time constant: Calculate the ramp with ΔVout = -VinΔt/(RC), and place a practical circuit’s lower corner below the intended integration band.
• Output voltage range: Include the initial condition, DC error and full signal excursion. Keep the result within the loaded output-swing range.
• Op-amp characteristics: Check supply, input common-mode range, gain-bandwidth product, loop gain, slew rate, offset, bias current, noise, output current and stability. Validate the complete circuit with worst-case component values.

For an ideal capacitor-feedback integrator, gain magnitude varies inversely with frequency:

This expression gives a 20 dB-per-decade decrease and a scale set by RinC. A practical integrator follows it only between its lower corner and the frequency where op-amp loop gain, phase shift, slew rate or noise exceeds the allowed error. Bench testing and simulation should cover the minimum and maximum signal conditions before the circuit is released.