- Half Adder Definition: A half adder is defined as a basic four-terminal digital device that adds two binary input bits, outputting a sum and a carry bit.
- Binary Addition: When adding binary bits, the half adder handles combinations like 0+0, 0+1, 1+0, and 1+1, with specific sum and carry results.
- Truth Table: The truth table for a half adder explains the sum and carry outcomes for each possible input combination.
- XOR and AND Operations: The sum is obtained using the XOR gate, and the carry is obtained using the AND gate in a half adder circuit.
- Half Adder Circuit Design: To explain a half adder with its truth table, the circuit design uses one XOR gate and one AND gate to achieve the required outputs.
A half adder accepts two binary inputs, A and B. Each input can be 0 or 1, so there are four input combinations: 0 + 0, 0 + 1, 1 + 0 and 1 + 1.
The two outputs together represent the ordinary binary result.
Decimal 2 is written as 10 in the binary number system. Therefore, 1 + 1 gives sum S = 0 and carry C = 1. The other three input combinations do not generate a carry. The truth table lists both outputs separately instead of treating 10 as a single output bit.
Half Adder Truth Table
| A | B | A + B | Decimal Output | Binary Output | Sum (A ⊕ B) | Carry (A ⋅ B) |
| 0 | 0 | 0 + 0 | 0 | 0 | 0 | 0 |
| 0 | 1 | 0 + 1 | 1 | 1 | 1 | 0 |
| 1 | 0 | 1 + 0 | 1 | 1 | 1 | 0 |
| 1 | 1 | 1 + 1 | 2 | 10 | 0 | 1 |
The truth table gives S = A ⊕ B, so the sum can be implemented with an XOR gate. It gives C = A · B, so the carry is an AND operation implemented with an AND gate. XOR is 1 only when A and B differ, while AND is 1 only when both inputs are 1.
Circuit of Half Adder
Using one XOR gate and one AND gate, the two equations form a half adder, as shown below. Because this circuit has no carry input, a multi-bit ripple adder normally uses a full-adder stage wherever a carry from a less-significant position must also be included.
