Shift Registers

Registers are devices used to store data bits. These bits can move within the registers or in and out by using clock pulses. Such registers are called shift registers. An n-bit shift register is formed by connecting n flip-flop, each storing one bit. A clear line resets each flip-flop, clearing the entire register.

Shift registers can be categorized based on the type of data movement.

• Category 1: Depending on the Direction of Data Shift
• Category 2: Depending on the Mode of Data In or Out

Category 1: Depending on the Direction of Data Shift

Unidirectional Shift Register

In this type, the data bits within the register can move only in one direction i.e. either towards left or towards right, accordingly they are called Left-Shift Register or Right-Shift Register (Figure 2).

Bidirectional or Reversible Shift Register

Bidirectional shift registers (Figure 3) can shift data in both directions, left and right. This is achieved by adding extra circuitry to unidirectional shift registers, including a control line to select the data shift direction.

Category 2: Depending on the Mode of Data In or Out

Serial In Serial Out (SISO) Shift Register

In case of serial in serial out shift registers (Figure 4a), both data loading as well as data retrieval processes are performed serially, in bit-by-bit fashion. Here for every clock pulse three functions are performed viz.,

1. One bit of data enters into the register,
2. Data within the register shifts either right or left by one bit,
3. One data bit will come out of the shift register.

However it is to be noted that valid data bit comes out of the n-bit SISO register only after the application of n clock pulses. Further one requires providing additional n clock pulses in order to retrieve the entire n-bit input word.

Serial In Parallel Out (SIPO) Shift Register

In serial in parallel out shift registers (Figure 4b), data is loaded into the register bit-by-bit while it is retrieved in parallel fashion. In this case, at every clock pulse

1. One bit of data enters into the register,
2. Data within the register shifts either right or left by one bit.

Meanwhile the output bits can be read-out in parallel, one bit from each of the individual register component. Further it is to be noted that valid n-bit data word comes out of the n-bit SIPO register just after the application of n clock pulses.

Parallel In Serial Out (PISO) Shift Register

In case of parallel in serial out shift registers (Figure 4c), the data loading happens in parallel fashion while the data retrieval is serial in nature. Here the entire input word enters into the shift-register at a single clock cycle. From then on, for each clock cycle.

1. Data within the register shifts either right or left by one bit
2. One bit exits the register.

This means that the data bits of the input word are obtained at the PISO output bit-by-bit. This indicates that in order to obtain the entire n-bit input word, one would have to wait for additional n clock cycles.

Parallel In Parallel Out (PIPO) Shift Register

In parallel in parallel out shift registers (Figure 3d) both data loading as well as data retrieval processes are parallel in nature. This means that the entire data word can be entered into the registers at a single clock tick. Similarly this entire data word can be obtained at the output pins of the individual register components by just providing one more clock pulse. However it is to be noted that these kinds of shift registers are also capable of shifting the data bits either towards right or towards left.

Further if the data-out pin of the shift-registers is back connected to the data-in pin, then the bits of the input word circulate within the registers without being lost.
Shift registers are useful when you need to reduce the number of control pins. For instance, to control 16 LEDs, you would need 16 lines from a microcontroller. Due to limited GPIO pins, this isn’t feasible. Using two shift registers in series can control the LEDs with just 4 I/O pins.
Shift registers are also used to convert serial data streams into parallel form and vice versa.