- SIPO Shift Register Definition: A Serial in Parallel Out (SIPO) shift register is a device that stores data serially and retrieves it in parallel.
- Data Shifting: Data bits move from one flip-flop to the next with each clock pulse, enabling sequential storage and parallel retrieval.
- Right-Shift Operation: In a right-shift SIPO register, data shifts from left to right with each clock tick.
- Left-Shift Operation: In a left-shift SIPO register, data shifts from right to left while maintaining the same working principle.
- Clock Pulse Dependency: The movement and storage of data depend on the rising edge of the clock pulse.
In Serial In Parallel Out (SIPO) shift registers, the data is stored into the register serially while it is retrieved from it in parallel-fashion. Figure 1 shows an n-bit synchronous SIPO shift register sensitive to positive edge of the clock pulse. Here the data word which is to be stored (Data in) is fed serially at the input of the first flip-flop (D1 of FF1). It is also seen that the inputs of all other flip-flops (except the first flip-flop FF1) are driven by the outputs of the preceding ones say for example, the input of FF2 is driven by the output of FF1. In this kind of shift register, the data stored within the register is obtained as a parallel-output data word (Data out) at the individual output pins of the flip-flops (Q1 to Qn).
Initially, the register contents are cleared by applying a high signal to the clear pins of all the flip-flops. Then, the first bit (B1) of the input data word is fed into the D1 pin of FF1.
This bit (B1) enters FF1, gets stored, and appears at its output Q1 on the first clock pulse. On the second clock pulse, B1 right-shifts to FF2 and appears at its output pin Q2 while a new bit, B2, enters FF1. With each clock tick, the data in the register moves one bit to the right, and a new input bit enters the register. The stored bits can be retrieved in parallel from the individual flip-flop outputs.
Similarly, the n-bit input data word becomes an n-bit output data word from the shift register at the rising edge of the nth clock pulse. The working of the shift register is summarized in Table I, and the corresponding waveforms are shown in Figure 2.
In the right-shift SIPO shift-register, data bits shift from left to right for each clock tick. However if the data bits are made to shift from right to left in the same design, one gets a left-shift SIPO shift-register as shown by Figure 3. Nevertheless the basic working principle remains the same except the fact that now Bn down to B1 is stored in Qn down to Q1 i.e. Q1 = B1, Q2 = B2 … Qn = Bn at the nth clock tick.
