- PISO Shift Register Definition: A PISO shift register is defined as a device that loads data in parallel format and retrieves it serially.
- Basic Components: A PISO shift register includes control lines, combinational circuits, flip-flops, and clock and clear pins.
- Loading Data: When the control line is low, input data is loaded in parallel through activated gates into the register.
- Shifting Data: With the control line high, data shifts right by one bit with each clock pulse, and it takes n clock cycles to get the entire n-bit data serially.
- Left-Shift Option: By modifying the design, data can be shifted from right to left, creating a left-shift PISO shift register with the same basic working principle.
A Parallel In Serial Out (PISO) shift registers loads a word in one clock and then sends it out one bit at a time. Figure 1 is a PISO shift register with a control line 
plus AND and OR gates around the flip-flops. Those stages still share clock and clear.
The 
line chooses load or shift. When that line is low, the A2 AND gates turn on and the A1 gates turn off.
The Data in bits on those A2 gates then pass through the OR gates of each stage. The first rising clock stores every bit (B1 goes straight into FF1). The whole word is therefore loaded on that one clock.
Next drive the line high. A1 gates turn on and A2 gates turn off. Each flip-flop then feeds the next stage through an OR gate, except the last stage FFn: the output of FF1 (Q1) is the output of OR gate 1 (O1) into D2; Q2 = output of O2 = D3 and so on. The next rising clock therefore moves Q1 to Q2, Q2 to Q3, … and Qn-1 to Qn.
That is a one-bit right shift. Each clock then sends one bit out of the nth stage (Data out = Qn of FFn). n clocks read the whole n-bit word.
Table I is the PISO shift register load-and-shift sequence. Figure 2 is the waveform.
Wire the chain the other way and the same control scheme becomes a left-shift PISO (Figure 3).
