- Parallel Adder Definition: A parallel adder is a digital circuit that adds multiple binary numbers simultaneously using full adders.
- 2’s Complement Addition: Binary subtraction is performed through 2’s complement addition, simplifying the circuit design.
- XOR Gates Function: XOR gates enable the circuit to switch between addition and subtraction modes based on the control line.
- Control Line (M-line): The M-line’s state (high or low) dictates whether the circuit performs addition or subtraction.
- Ripple Propagation Delay: A drawback of the parallel adder-subtractor is the ripple propagation delay, affecting computation speed.
An n-bit combinational circuit can use one chain of full adders, as in a Parallel Adder, while also performing the work of a Parallel Subtractor. The resulting parallel adder or subtractor selects either A + B or A – B.
For two’s-complement binary numbers, A – B equals A + NOT B + 1. A control input can select addition or conditionally invert B and supply the extra 1 for subtraction.
The circuit forms the 2’s complement by placing one XOR gates stage on each B input and connecting the same mode signal to the least-significant carry input. Together, these connections either pass B unchanged or invert B and add 1.
The M-line selects the operation. With M = 0, every XOR gate receives a control 0 and passes each bit of 
unchanged. The carry input Ci1 of the least-significant full adder FA1 is also 0, so the circuit adds 
and 
.
With M = 1, each XOR gate receives a control 1 and complements the corresponding bit of 
. The carry input is also high.
The circuit complements the binary number before it enters the full adders. With Ci1 high, the least-significant full adder FA1 supplies the added 1 needed for two’s complement. The chain then subtracts 
from . The final carry and signed-overflow interpretation depend on whether the operands are unsigned or two’s-complement values.
Drawback of Parallel Adder or Subtractor
In this parallel adder-subtractor, each carry must pass through the preceding stage before the most-significant result settles. This ripple-carry path makes delay grow with word length, as it does in a basic parallel adder. Faster adder structures reduce that delay when the extra logic is justified.
