- Parallel Adder Definition: A parallel adder is a digital circuit that adds multiple binary numbers simultaneously using full adders.
- 2’s Complement Addition: Binary subtraction is performed through 2’s complement addition, simplifying the circuit design.
- XOR Gates Function: XOR gates enable the circuit to switch between addition and subtraction modes based on the control line.
- Control Line (M-line): The M-line’s state (high or low) dictates whether the circuit performs addition or subtraction.
- Ripple Propagation Delay: A drawback of the parallel adder-subtractor is the ripple propagation delay, affecting computation speed.
We learned about parallel adder circuits, which use cascaded Parallel Adder, and Parallel Subtractor, which can be designed in two ways. For optimization, it’s better to use a single circuit for multiple operations. So, we need to consider if we can perform both n-bit addition and subtraction with one digital circuit—a parallel adder or subtractor.
The answer is yes. This is because, the subtraction process of binary numbers is nothing but their 2’s complement addition.
Therefore, a parallel adder can be adapted to provide the 2’s complement of a number, allowing it to function as both an adder and a subtractor. This design uses XOR gates, as shown in Figure 1.
Here M-line acts as a control line i.e. depending on the value provided at M, the circuit behaves either as an adder or as a subtractor. The reason for this can be explained below. Suppose, if M-line is driven low, then one of the input to each and every XOR gate would be logic 0. This means that the XOR outputs in this case will be unaltered binary bits of the number 
. In addition, if M = 0, the carry in pin (Ci1) of the first full adder (FA1) would also be 0. Due to these conditions, the circuit shown will be behave as a n-bit adder adding the number 
with 
.
Similarly let us now analyze the case where M = 1, meaning which the M control line is pulled high. In this case, one of the inputs to each XOR gate would be logic 1. This means that we get the complement of the bits 
as the outputs of each XOR gate.
This indicates that the binary number is complemented before being fed as an input to each of the full adder in the circuit. In addition, for the same case, even the Ci1 of the first full adder FA1 would be logically high. As a result, the cascaded arrangement of full adders shown in Figure 1 effectively performsn-bit binary subtraction wherein the binary number 
is subtracted from .
Drawback of Parallel Adder or Subtractor
The architecture of the parallel adder-subtractor is similar to both parallel adder and subtractors, so it also suffers from ripple propagation delay. Despite this, these circuits are used in computers’ arithmetic and logic units (ALU) for various computations.
