- Binary Subtractor Definition: A binary subtractor is a digital circuit used to subtract two binary numbers and provides outputs of the difference and potential borrow.
- 2’s Complement Subtraction: This essential subtraction method involves inverting the bits of the subtrahend, adding one, and then adding it to the minuend to calculate the difference.
- 4 bit subtractor: A 4 bit subtractor specifically handles subtraction of binary numbers up to four bits in length, simplifying the operation by directly addressing each bit.
- Half vs. Full Subtractor: A half subtractor subtracts single bits and provides a difference and borrow, whereas a full subtractor extends this functionality to multi-bit binary numbers.
- Circuit Complexity: Understanding the use of logic gates and K-maps in subtractors helps clarify how subtractors are designed to manage binary subtraction efficiently.
A binary subtractor can implement subtraction directly with borrow signals or reuse an adder through two’s-complement arithmetic. Start with the rules for subtracting two multi-bit binary numbers.
For one bit position, subtract the subtrahend bit and any borrow-in from the minuend bit.
If the minuend bit is too small, borrow 1 from the next more-significant position. In base two, that borrowed unit contributes 2 to the current position, and the borrow-out becomes the borrow-in for the next position.
Digital hardware often performs the same operation with the 2’s complement of the subtrahend.
For fixed-width two’s-complement subtraction A – B, leave A unchanged, invert every bit of B and add 1. The resulting value is then added to A. Keep the same bit width throughout.
In the six-bit example, A = 110011 and B = 100101.
The binary number 100101 becomes 011010 after bit inversion. This is its 1’s complement. Adding 1 gives the six-bit two’s complement 011011.
Adding 110011 to the 2’s complement 011011 gives 1 001110. In a six-bit result, discard the carry beyond the fixed width, leaving 001110, which is decimal 14.
The same method scales to the four-bit adder-based circuit shown below.
Here A4, A3, A2 and A1 form the minuend, while B4, B3, B2 and B1 form the subtrahend. S4, S3, S2 and S1 form the fixed-width result. Discard final carry-out C4 for the fixed-width two’s-complement value; an unsigned design may instead use it to derive borrow status.
Half Subtractor
A half subtractor subtracts one subtrahend bit B from one minuend bit A. It has no borrow-in input, and it produces difference D plus borrow-out b.
The truth table lists all four combinations of A and B.
The truth table gives D = A XOR B. Borrow-out is 1 only for A = 0 and B = 1, so b equals NOT A AND B.
These equations map directly to XOR, NOT and AND gates.
The circuit therefore handles the least-significant position only when no external borrow-in is required.
Full Subtractor
A full subtractor handles one position in multi-bit direct-borrow subtraction. It accepts minuend bit A, subtrahend bit B and borrow-in bi from the less-significant position. It outputs difference D and borrow-out b for the next more-significant position. Cascading one stage per bit allows the borrow to ripple from right to left.
A half subtractor cannot accept borrow-in. A full subtractor adds this third input and can be built from two half subtractors plus an OR gate. This direct-borrow circuit is different from the adder-based two’s-complement circuit described below.
The truth table lists the eight combinations of A, B and bi and their D and b outputs.
A K-map reduces the two output functions.
The difference output is A XOR B XOR bi. Borrow-out is asserted when A is smaller than B + bi for that bit position.
Binary Adder Subtractor
A four-bit adder and a two’s-complement binary subtractor can share the same full-adder chain. A mode input M controls both the B-bit inversion and the initial carry-in.
When M = 0, each B input passes unchanged and the least-significant carry-in is 0, so the circuit calculates addition. When M = 1, B1, B2, B3 and B4 are inverted, while M supplies carry-in 1 to add the second part of the two’s complement.
The control works because XOR passes a data bit when M = 0 and complements it when M = 1. The same rule applies to B1, B2, B3 and B4.
An XOR gate is therefore placed before every B1, B2, B3 and B4 input, with M connected to the other XOR input.
For M = 1, B1, B2, B3 and B4 are complemented and the full-adder chain calculates A + NOT B + 1, which equals A – B at the selected bit width. M must feed the least-significant carry-in, not a borrow input.
