- Parallel Adder Definition: A parallel adder is defined as a circuit that combines several full adders to add multi-bit binary numbers.
- Structure of Parallel Adder: A parallel adder consists of a series of full adders, each handling a bit of the binary numbers.
- Input and Carry Connections: Each bit is input into corresponding full adders, with carry outputs linked to carry inputs of the next adder.
- Ripple Carry Effect: The carry propagates through the chain of adders, causing a delay known as carry propagation delay.
- Drawback of Parallel Adders: The carry propagation delay increases with the number of bits, slowing down the addition process.
Adders are combinatorial circuits used to add two binary numbers. The type of adder depends on the characteristics of the numbers. For adding two single-bit numbers, a half adder is used. If there is an additional carry, a full adder is used. For adding multi-bit binary numbers, a parallel adder is needed.
Structure of Parallel Adder
A parallel adder is a series of full adders connected in a cascade. The number of full adders matches the number of bits in the binary numbers to be added.
Such a n-bit adder formed by cascading n full adders (FA1 to FAn) is as shown by Figure 1 and is used to add two n-bit binary numbers 
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Here, every single bit of the numbers to be added is provided at the input pins of every single full adder. That is, the first bits A1 and B1 are provided as the inputs to full adder (FA1), the second bits A2 and B2 to the inputs of full adder 2 (FA2)… and the last bits An and Bn to the nth full adder FAn. Next, the carry out pin of each full adder in the circuit is connected to the carry in pin of its succeeding full adder (except in the case of last full adder). For example, the carry out pin of FA1 (Co1) is connected to carry in pin of FA2 (Ci2), the carry out pin of FA2 (Co2) is connected to carry in pin of FA3 (Ci3) and so on and so forth.
Working of Parallel Adder
In the circuit shown by Figure 1, first, FA1 adds A1 with B1 to generate S1 (the first bit of sum output) and Co1. Next, FA2 uses this Co1 as its carry in bit and adds it with its input bits A2 and B2 to generate the second bit of the sum output S2 and Co2. Next, this Co2 is considered as an input by FA3 which adds it with the bits A3 and B3. This process continues till the nth full adder in the sequence which adds the carry out bit of (n-1)th full adder (Con-1) with its inputs An and Bn. When this happens, we would get the output bits Sn and Con which are the last bits of our sum output and the expected carry bit, respectively.
Drawback of Parallel Adders
From the discussion presented we can say that in the case of n-bit parallel adder, each adder has to wait for the carry term to be generated from its preceding adder in order to finish its task of adding. This can be visualized as if the carry term propagates along the chain in the fashion of a ripple. Thus these kind of adders are even referred to as ripple carry adders.
Further, the delay associated with the travelling of carry bit is called carry propagation delay and is found to worsen with an increase in the length of the binary numbers which require to be added. For example, if each full adder is considered to have a delay of 10 ns, then the total delay required to produce the output of a 4-bit parallel adder would be 4 × 10 = 40 ns.
