- NMOS Logic Definition: NMOS logic is defined as a logic family using N-channel MOSFETs, offering higher density and speed for digital circuits.
- PMOS Logic Definition: PMOS logic is defined as a logic family using P-channel MOSFETs, which perform logic functions using positive and negative voltages.
- PMOS Inverter Function: In PMOS logic, an inverter uses a P-channel MOSFET as a load, with GND representing logic ‘1’ and -VDD representing logic ‘0’.
- NMOS Advantages: NMOS logic is preferred for its smaller chip area and higher speed due to better charge carrier mobility.
- Logic Gate Variations: NMOS logic includes variations like VMOS, DMOS, and HMOS, aimed at reducing propagation delay and improving performance.
SSI and MSI chips still ship logic gates, flip flops, counters, multiplexers and demultiplexers. Those parts sit at small-scale and medium-scale integration.
TTL and ECL used too much area and power for early MOS-scale LSI. CMOS later became the VLSI family. In the MOS-LSI years the dense options were PMOS, NMOS and bipolar I2L. This page covers PMOS and NMOS load-plus-switch logic.
PMOS Logic
The PMOS logic family uses P-channel MOSFETs. Figure (a) shows an inverter circuit using PMOS logic (not to be confused with a power inverter). MOSFET Q1 acts as an active load for the MOSFET switch Q2.
GND and −VDD respectively represent a logic ‘1’ and a logic ‘0’ for a positive logic system. When the input is grounded (logic ‘1’), Q2 remains in cut-off and −VDD appears at the output through the conducting Q1. When the input is at −VDD or near −VDD, Q2 conducts and the output goes to near-zero potential (logic ‘1’). Figure (b) shows a PMOS logic based two-input NOR gate. In Fig.(b) the output goes to logic ‘1’ (ground) only when both Q1 and Q2 are conducting.
Both inputs must then be logic ‘0’. For every other input pair the output sits at logic ‘0’, because with either Q1 or Q2 off the output is nearly −VDD through the conducting Q3. Fig.(b) is therefore a two-input NOR in positive logic.
The load MOSFET [Q1 in Fig. (a) and Q3 in Fig. (b)] is sized so its ON-resistance is much greater than the total ON-resistance of the switch MOSFETs [Q2 in Fig. (a) and Q1 and Q2 in Fig.(b)].
NMOS Logic
The NMOS logic family uses N-channel MOSFETs. N-channel MOS devices need a smaller chip area per transistor than P-channel devices of that era, so NMOS packed denser. Higher mobility of the charge carriers in N-channel devices also made NMOS faster than PMOS.
That density and speed is why 1970s MOS memories and microprocessors used NMOS, then scaled NMOS (HMOS). Older texts also list VMOS and DMOS as faster MOS structures. Figures (a) and (b) plus (c) show an NMOS inverter, a two-input NOR and a two-input NAND.
