Binary Decoder: What is it? (Truth Table And Logic Diagram)

Contents

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Key learnings:

Binary Decoder Definition: A binary decoder is a logic circuit that converts n binary inputs into 2^n unique outputs.
Truth Table: A truth table shows the output states of a decoder for every possible input combination.
Enable Pin: The decoder operates only when the enable pin is high; otherwise, all outputs are low.
Output Logic: For each input combination, a specific output line goes high, demonstrating the decoder’s function.
Basic Binary Decoder Applications: Used in data multiplexing, seven-segment displays, and other digital systems.

What is a Binary Decoder?

A binary decoder is a combinational logic circuit that maps an n-bit input code to one of up to 2ⁿ output lines. The selected output level and enable condition depend on the circuit. Decoders are used for address selection, data multiplexing, demultiplexing and seven segment displays.

In a one-of-N decoder, the binary value on the input lines selects one output line.

The circuit therefore maps each valid input code to a defined output condition.

Signal polarity matters. Some devices assert the selected output high, while others assert it low. Enable inputs can also be active high or active low.

The following active-high example shows the basic decoding operation.

Figure 1 shows one active-high enable input and three binary select inputs. Three input bits can select one of eight outputs because 2³ = 8.

A decoder’s truth table lists the output condition for every combination of select and enable inputs.

Table I applies to the active-high circuit in Figure 1. When its enable input is low, every output is low regardless of the select code. This disabled behaviour is not universal; an active-low decoder can hold all outputs high when disabled.

A low enable places this example in its disabled condition. A combinational decoder has no stored value to reset.

For this example, the enable input must be high before an output can be selected.

With the example enabled and I₂I₁I₀ = 000, output O₀ is high while O₇ through O₁ remain low.

For input code 001, only O₁ is high. Each remaining code selects the output with the corresponding binary index:

O₂ is high for 010, O₃ for 011, O₄ for 100, O₅ for 101, O₆ for 110 and O₇ for 111.

boolean equations for the outputs of the 3 to 8 decoder

The image above gives the Boolean equations for the active-high three-to-eight decoder in Figure 1.

3 to 8 binary decoder circuit diagram logic gates

Equations (1) to (8) can be implemented with an AND gate for each output and shared NOT gate stages, as Figure 2 shows.

Each output is the AND of the enable signal and the required true or complemented form of every select input. The blue lines carry true inputs, the red lines carry complements and the black line carries enable.

The same one-of-2ⁿ selection principle applies to a general n-input decoder.

A physical decoder may provide fewer than 2ⁿ outputs or use different enable and output polarities, so its truth table and data sheet control.

Common applications include memory address decoding, chip-select generation, data routing and code conversion for a seven segment display.