Key learnings:
- Universal Shift Register Definition: A universal shift register is defined as a register that can load and retrieve data in both serial and parallel modes, shifting data left or right.
- Modes of Operation: The shift register can function in multiple modes (serial-in serial-out, serial-in parallel-out, parallel-in serial-out, parallel-in parallel-out) depending on the select lines.
- Multiplexer Connections: Each 4×1 multiplexer connects to a flip-flop with inputs for holding current data, shifting right, shifting left, and parallel loading.
- Truth Table and Waveforms: The truth table and waveforms illustrate the different operating states and data shifts within the register.
- Applications: Universal shift registers are crucial for efficient data storage, transfer, and manipulation in digital circuits.
A Universal Shift Register can load and read bits in serial or in parallel and can shift them left or right. It is the four one-way modes (SISO, SIPO, PISO, PIPO) plus a bidirectional shift register and a parallel-load path in one block. That combination is a universal shift register. Figure 1 is an n-bit shift register of this kind.
Figure 1 uses n 4-to-1 multiplexers, one on each flip-flop D input. The stages share clock and clear. All multiplexers share select lines S1 and S0, which pick the mode.
- First input (Pin Number 0) connected to the output pin of the same flip-flop i.e. zeroth pin of MUX1 is connected to Q1, zeroth pin of MUX2 is connected to Q2, … zeroth pin of MUXn is connected to Qn.
- The second input (Pin 1) of each multiplexer connects to the output of the previous flip-flop. For instance, MUX2’s Pin 1 connects to Q1, MUX3’s Pin 1 connects to Q2, and so on. The first flip-flop (FF1) uses this pin as a serial input for right shifts.
- Third input (Pin Number 2) connected to the output of the very-next flip-flop (except the first flip-flop FFn where it acts like an serial-input to the input data bits which are to be shifted towards left) i.e. second pin of MUX1 is connected to Q2, second pin of MUX2 is connected to Q3,… second pin of MUXn-1 is connected to Qn.
- Fourth input (Pin Number 3) connected to the individual bits of the input data word which is to be stored into the register, thus providing the facility for parallel loading.
Table I lists the modes of this shift register. Table II is the truth table. Figure 2 is the waveform.
