- Programmable Array Logic Definition: Programmable Array Logic (PAL) is a type of Programmable Logic Device (PLD) used to implement specific logical functions.
- Structure and Components: PALs have an AND gate array followed by an OR gate array, with only the AND gate array being programmable.
- Programming Mechanism: Inputs are connected to the AND gates through a programmable matrix, allowing users to set specific connections.
- Logic Function Realization: The outputs from the AND gates are fed to fixed OR gates, resulting in logic functions in sum-of-products form.
- Programming Languages Used: PALs can be programmed using languages like PALASM, CUPL, and ABEL.
Programmable Array Logic (PAL) is a type of Programmable Logic Device (PLD) used to implement Boolean functions. In the classic PAL architecture, a programmable AND array generates product terms and fixed routing assigns those terms to each OR gate. Programmable links select true or complemented inputs for the AND gates. A PLA differs because both its AND and OR arrays are programmable. Later PAL-compatible devices can add output macrocells, registers, feedback and programmable output control.
Figure 2 uses m inputs, p product terms and n outputs to illustrate the classic structure. Buffers and inverters make the true and complemented form of each input available to the programmable matrix. Each product-term AND gate has candidate crossings for those literals, and programming selects only the connections required by its Boolean expression.
The red matrix contains the programmable links. A product term connects to the true or complemented form of each required input. An input omitted from that term remains disconnected and acts as a don’t-care condition. The resulting AND-array outputs feed assigned OR gates through the fixed routing shown in blue. Every product term does not necessarily reach every OR gate. In this example, output O1 combines several terms, including the output of AND gate 1 (A1), AND gate 2 (A2) and AND gate p (Ap).
In the illustrated example, OR gate n (On) receives terms A1 and Ap. A design must fit its equations into the product terms allocated to each output.
The n output functions are expressed in sum-of-products (SOP) form, so the diagram can be described as an m-input, p-product-term, n-output PAL. A real device has a fixed number of input pins, product terms and OR gates, along with defined routing between them. A compiler must therefore fit a design such as 3 inputs, 8 AND gates and 4 outputs into the resources of a selected part.
Programming technology depends on the part. Classic fuse-based PALs are normally programmed once. PAL-compatible GAL and modern SPLD devices can use erasable non-volatile cells. A design tool compiles Boolean equations or supported HDL source into a device-specific JEDEC programming file, and a compatible programmer writes that file to the PAL or replacement device. PAL assembler (PALASM) and Advanced Boolean Expression Language (ABEL) are legacy languages. CUPL remains available for supported Microchip PLDs.
