Astable Multivibrator: A Free-Running Oscillator Circuit

What is an Astable Multivibrator?

An astable multivibrator is a free-running oscillator with no stable output state. After power is applied, feedback makes it alternate continuously between two temporary states without a recurring external trigger. Its output is usually a rectangular waveform rather than a perfect square wave. The other main multivibrator modes are the one-stable-state monostable multivibrator and the two-stable-state bistable multivibrator.

A multivibrator uses two amplifying or switching stages connected by feedback. In the discrete transistor circuit below, cross-coupling capacitors create the rapid state changes. Collector-load and base-bias resistors provide current paths and set the timing with the capacitors. Other astable circuits use logic gates, operational amplifiers or timer ICs, with equations specific to each topology.

The two outputs of a symmetrical transistor astable are approximately complementary: when one collector is high, the other is low. Component values set the two state intervals, so they control frequency and duty cycle. Transistor thresholds, saturation voltage, resistor and capacitor tolerances, supply variation and temperature cause real values to differ from simple calculations.

How does an Astable Multivibrator work?

The diagram shows a cross-coupled astable multivibrator made with two bipolar junction transistors (BJTs):

Q1 and Q2 act as switches. RC1 and RC2 are collector-load resistors. R1 and R2 supply base current and form the timing paths with C1 and C2. Each capacitor connects one collector to the opposite base. A sudden collector change is therefore coupled to the other transistor, while slower charging and discharging through a base resistor determines when the next change occurs.

The following sequence assumes Q2 turns on first. The labels refer to the diagram above.

• Small differences in transistor gain, noise or component values break the apparent balance at power-up. Positive feedback quickly drives one transistor towards saturation and the other towards cutoff.
• Assume Q2 saturates first. Its collector voltage falls close to its saturation level, while collector current flows through RC2. Q1 remains off and its collector rises towards Vcc through RC1.
• The downward step at Q2’s collector passes through C2 to Q1’s base. This drives the base negative relative to its previous value and holds Q1 off. Capacitor voltage cannot change instantly, but the voltages at both terminals can step together.
• During this temporary state, output O1 is high and output O2 is low. Neither state is stable because a timing capacitor is recovering through its base resistor.
• C2 now charges through R2 towards Vcc, so Q1’s base voltage rises exponentially from its negative starting value. C1 settles to the voltage associated with Q1 off and Q2 on.
• When Q1’s base reaches roughly its base-emitter turn-on voltage, current begins forward biasing the junction. Q1 collector current increases and its collector voltage starts to fall.
• As Q1 turns on, its collector voltage drops quickly. C1 couples this negative-going step to Q2’s base, reducing Q2 base current and starting the opposite transition.
• Q2 turns off and its collector rises through RC2. That rising collector voltage, coupled through C2, further drives Q1 on. This regenerative feedback makes the transition much faster than the RC charging interval.
• The circuit is now in its opposite temporary state: O1 is low and O2 is high. Q1 is near saturation while Q2 is near cutoff.
• C1 charges through R1, causing Q2’s base voltage to rise exponentially from its negative value. C2 settles for the new collector levels.
• When Q2’s base reaches its turn-on voltage, Q2 collector current begins to rise and its collector voltage begins to fall.
• The falling Q2 collector voltage couples through C2 to Q1’s base. Q1 loses base drive and turns off, while its collector rises through RC1.
• The rising Q1 collector voltage couples through C1 and reinforces Q2’s turn-on. The circuit returns rapidly to the first temporary state.
• One full cycle is complete when O1 is high and O2 is low again. The alternating RC recovery and regenerative transitions continue while supply and component limits are satisfied.

The period T is the time for both temporary states. Frequency f is the reciprocal of the period, f = 1/T. Duty cycle must name the observed output and the state counted as active because the two collectors have opposite polarity. For O1, for example, the high-time duty cycle is its high interval divided by T.

How to calculate the frequency and duty cycle of an Astable Multivibrator?

For the labelled BJT circuit, a common first estimate is t1 ≈ 0.69 R1C1 and t2 ≈ 0.69 R2C2, giving T ≈ t1 + t2 and f ≈ 1/T. Exact timing depends on Vcc, base-emitter and saturation voltages, transistor gain and the collector circuits. The two legacy images below use an R1 + R2 term for t1, which does not match the timing paths in the BJT diagram above. Do not apply those image equations to that circuit without deriving its actual current paths.

• Legacy frequency expression retained for reference:

• Legacy duty-cycle expression retained for reference:

Use these approximate definitions for the BJT schematic instead:

• t1 ≈ 0.69 R1C1: one state interval set by the R1-C1 timing path
• t2 ≈ 0.69 R2C2: the other state interval set by the R2-C2 timing path
• T ≈ t1 + t2 and f ≈ 1/T
• For the output whose high interval is t1, D ≈ t1/T; the complementary output has the opposite duty cycle

A 555 timer uses a different astable circuit and different equations. Pins 2 (trigger) and 6 (threshold) monitor the same timing capacitor. The capacitor charges through R1 and R2, then discharges through R2 and the internal transistor at pin 7. Pin 4 (reset) must be held high for normal operation. A small bypass capacitor from pin 5 (control) to ground can improve noise immunity when the datasheet recommends it. Pin 8 is Vcc and pin 1 is ground. The bipolar NE555 output can source or sink substantial current, but the often-quoted 200 mA is a capability limit under stated conditions, not a default load target or a guarantee of rail-level output.

The standard 555 astable cycle works as follows:

• With the discharge transistor off, timing capacitor C charges towards Vcc through R1 + R2. The trigger and threshold comparators monitor its voltage against levels near one-third and two-thirds of Vcc.
• When C rises to about two-thirds of Vcc, the threshold comparator resets the internal latch. Output pin 3 goes low and the discharge transistor at pin 7 turns on, providing a low-impedance path towards ground.
• C then discharges through R2. When its voltage falls to about one-third of Vcc, the trigger comparator sets the latch. Pin 3 goes high and the discharge transistor turns off, so C starts charging again through R1 + R2.
• The cycle repeats without an external trigger. In the standard circuit, output high time is approximately 0.693(R1 + R2)C and output low time is approximately 0.693R2C. These relations assume the standard thresholds and neglect component tolerances and propagation delays.

The following 555 equations therefore apply to the standard R1-R2-C astable connection. Check the selected 555 datasheet when frequency is high or when a diode, control voltage or different discharge path changes the topology.

• Frequency:

• Output-high duty cycle:

Conclusion

An astable multivibrator alternates continuously between two temporary states and produces a periodic waveform. Cross-coupled transistors, logic gates, op amps and 555 timers can implement this behaviour, but each circuit has its own timing paths and equations. For the discrete BJT circuit, the two base-resistor and capacitor products set the approximate state intervals. For the standard 555 circuit, the capacitor charges through R1 + R2 and discharges through R2.

These circuits can provide clocks, indicator flashes, alarms, tone sources and test pulses. Before using one, define frequency, output-high duty cycle, voltage levels, load current and acceptable tolerance. Then include device thresholds, resistor and capacitor tolerance, temperature, startup behaviour and output loading in the design check.