- Master Slave Flip Flop Definition: A master slave flip flop is defined as a combination of two flip-flops where the first is the master and the second is the slave.
- Triggering Mechanism: The master flip-flop is triggered by an external clock pulse, while the slave flip-flop is triggered by the inverted clock pulse.
- Pulse-Triggered Operation: The master slave flip flop, also known as a pulse-triggered flip-flop, completes its operation after one full clock pulse.
- Truth Table of Master Slave Flip Flop: The master slave flip flop truth table illustrates the timing of the master and slave outputs, with the slave output being delayed by half a clock cycle.
- Structure: The flip-flop consists of NAND gates and an inverter, with a master part and a slave part.
A master slave flip flop is two flip-flops in series: a master and a slave (Figure 1). The master flip-flop is enabled by the external clock. The slave is enabled by the inverted clock. Data enters the master on one half of the clock pulse and appears at the outputs on the other half. The pair finishes one transfer in one full clock pulse, so it is also called a pulse-triggered flip-flop.
Figure 2 shows a master-slave JK flip-flop built from NAND gates and an inverter that complements the clock. NAND gate 1 (N1) takes the external clock, input J and output Q̅. NAND gate 2 (N2) takes the external clock, input K and output Q.
The outputs of N1 and N2 feed the cross-coupled gates N3 and N4. Those four gates (N1, N2, N3 and N4) are the master. The slave is the same arrangement of N5, N6, N7 and N8.
The slave is driven by the master outputs M1 and M2, which is why the circuit is a master-slave flip-flop. While the clock is high the master is enabled, so M1 and M2 follow J and K. The outer outputs stay still because the slave is disabled on that half of the pulse. When the clock is low the master is disabled and the slave copies M1 and M2 onto Q and Q̅.
Table I is the truth table for the flip-flop in Figure 2. The master outputs (red boxes) change while the clock is high (red arrow). The slave outputs stay latched then. The slave copies that data to the outer pins (blue boxes) when the clock is low (blue arrow). Figure 3 is the timing diagram of the master-slave flip-flop. The green arrows mark the slave output as the master output delayed by half a clock cycle.
Other master-slave types follow the same two-stage clocking as this JK example.
